In order to play around with and test signal transmission across the backplane I need a means to inject and detect signals... and so the apricot card was designed.
Like all the alpha series cards, on the left side is the din 41612 connector that binds the power and signal lines to the backplane and one the bottom is the msp430 controller. The controller is linked to a common i2c bus and has it's own 3v3 ldo. The controller handles the enable lines for the other power supplies and other components on the board.
One the top are the larger power supplies for the fpga (2v5 and 3v3). Their output is connected to elecrolytic caps to buffer larger current fluctuations. Bank 0 on the fpga is locked to 3v3 but banks 1,2 and 3 can be set to either 2v5 or 3v3 with jumpers.
One the right side two sma-rp connectors are connected to the fpga on separate banks. These can be used to bring signals in or out over a 50 ohm line. There are also 6 signal lines on a sip breakout.
The fpga I chose here was a spartan-3an (144 tqfp, 50Kgates) to bind both the dingle ended and differential signal lines from the bus. It's small for an fpga, but the primary purpose here is to inject and receive signals from the bus for testing. Having the flash on the chip makes it easier to route (hard enough to route this on 2 layers as it is - 4 would have been a lot easier). Bringing the jtag lines out provides a means to program it and connecting the configuration lines to the msp430 controller provides a means to restart or disable it on demand. A separate jumper is used to lock it in program mode when needed. The fpga is also diectly connected to the spi bus run bu the backplane controller.
The top copper layer contains a few cutouts in the fill layer to prevent encroachment of the ground on the differential pairs... Most of them could be routed as I prefer but a few had to be compromised but having a signal line run close to one of the pairs or routing a pair through vias... It will be interesting to see how much this actually matters in reality.
The bottom copper layer handles far fewer signals (mostly power). The 50 MHz oscillator is mounted near the bottom and crosses tangent to the signal lines it must. The bottom also contains the 1v2 ldo for the fpga and the decoupling networks for the io banks.
The organizational layout is easier to see looking at the silkscreens - this is the top...
and this is the bottom silkscreen. The 2v5 ldo runs off the 3v3 - both have nice electrolytics as buffers. The 1v2 uses a tantalum instead right nest to the rest of the decoupling network. The values of these caps I may adjust after I see the noise quality of the power line.
Well, that's the quick overview... the boards are sent out so hopefully soon I can put one together and have some fun... The only other comment I want to make it that the last thing I like to do when the layout and routing is finished is to use thin lines to trace out the ground paths across the board... One of the hardest things to troubleshoot later is having a ground connection that ended up insufficient on a component... usually only appears as unpredictable intermittent errors when under load (either currect or rf/switching).
As usual, the schematics and board files and gerbers are here,