Friday, May 27, 2011

Apricot cards arrive...

Yay, another new board in the mail... This time it's the apricot card for the alpha backplane.  I used Laen's service (DorkbotPDX) so I got 3 copies of the design.   Quick electrical tests (resistance between linked pins and unlinked pins) look correct.  I did make a stupid mistake with the hole sizes for the sma connectors (I really should just always make my own components every time). This card contains the usual msp430 board controller for the alpha series backplane, but also a tiny happy fpga (Xilinx spartan 3AN) so I can begin exploring signals (bound to all the single ended and differential lines).  There are multiple additional power supplies here that are controlled by msp430 (the microchip MCP1825 for 2v5 is in the upper right)

On the backside is the 1v2 core ldo and the rest of the power routing to the fpga - decoupling caps for the core and io banks take up the middle region.  Off the left is the microchip MCP1826 regulator for 3v3 (much higher current and controlled by the msp430).

The copper layer is excellent and the solder mask is almost as good (spoiled I am by whoever fabs these boards - always say it because it's always true). 

No copper errors on any of the 3 boards, no anomalies in the thickness or placement, no bleeds from the copper fills, holes are easily within spec for position and size.  The silkscreen is a much lower resolution but easily legible enough on the tiniest letters for assisting placement.

I can never really tell with vias in fill zones whether they are plated through - they always seem to work - I always get that moment of fear that they aren't because it's so easy to see the plating on the larger holes with annulars... with some manufacturers I can see a raised bump from the vias in fill regions, this one is just flat.  I also like the fact that the mask doesn't randomly fill the vias (I really don't like to see that).

I left out the sma connectors (because I botched the hole sizes in the design) but the rest of the components are in... yay...  One the bottom is the DIN 41612 connector (This one is Molex - it doesn't have the retention clips but surprisingly it stayed perfectly in place when soldering because of the card edge tension... nice when parts hit spec).   Just above that are the differential termination resistors (I'm starting with them at 150 ohms but this will likely change as testing begins - the alpha backplane is 2 layers with intended characteristic impedance targets for the signal lines between 148 and 152 ohms, differentials closer to 180 (these are far from the ground plane and tightly coupled).  I'm not certain what the actual imp. will be or how much it will change depending on slot population (which is what testing ought to reveal) but eventually after I get some real world data the act/dyn impedance control designs can begin... Single ended lines are not terminated on this card.

On the bottom right is the little ldo (3v3 always enabled) for the msp430 controller - I like to use the micrel MIC5205's for this - low noise, easy, simple, always works.  Above that is a small ceramic filter cap and a standard resistor/led combo (I don't usually put leds on all the power supplies but when there isn't an enable control for them I do - saves trouble shooting and drains the caps once the power is cut).  This 3v3 supply feeds the msp430 controller just above (socket is empty here) and fills the electrolytic cap on the top (but backside) of the board.  Above the controller socket are the filter caps and the pullup resistor for reset (needed by the sbw programmer - just tap a launchpad - works great and cheap).

In the center is the Xilinx Spartan 3AN fpga (just a tiny one - but enough for this).  Near by are the split jtag interface and a jumper for PUCD.   This fpga has an internal flash so I don't have to add a separate prom image - yay.  There are four io banks, 1 is locked to 3v3 (backplane SPI/I2C is 3v3) but the others are switchable (jumpers on the left side).  Some pins are brought out for external use on the top as well as 2 sma connectors (but remember I botched the hole sizes so they are left unpopulated).  The 2v5 regulator is on the lower left side as well as it's filter and bulk caps. 

On the back side we find the 3v3 regulator for io banks (controlled by the msp430) in the upper right side and the bulk caps for the 2v5 and 3v3 bank io supplies.  The center has the filter cap arrays (4 banks and logic) and the 1v2 core logic ldo with a 100 uf Tantalum cap).   In the upper left is the 50 MHz oscillator.  I haven't washed the board yet so the flux around the DIN 41612 connector is visible around the pins.

Here's we have the apricot and the niblet termination boards on the alpha backplane... yay signal testing soon...