Saturday, February 19, 2011

Clocks and logic...

When one has a "clocked" circuit the only important thing to know is that the clock determines the moment in time that the logic component determines the output.  While the logic component may use many separate signals internally, there will always be one signal that represents the output of that logical network and so in all clocked circuits it comes down to mixing a single clock source and a single logic source into a single output... In a simple case one could have a logical element that mirrors the clock signal when the logical source is high and drives the output low when the logical element is low.   If the green (logical) signal were shifted slightly to the right in this case, the red (output) signal would still look exactly the same.  Only if it was shifted enough to the left or the right such that the first or third posedge overlapped the high level of the logic source would the output be different.

One could also set things up so that the output simply mirrors the logic source but changes can only happen on when the clock signal is rising (posedge).  If the green (logical) signal were shifted slightly to the right in this case, the red (output) signal would still look exactly the same.  Only if it was shifted enough to the left or the right such that the first or third posedge overlapped the high level of the logic source would the output be different.

There isn't really a way for this to be a correct set of relationships because the the relationship is not consistent... While it is possible to have the output change based on both the increasing and decreasing edges of the clock for the same logic source, the relationship must be the same in all cases.  If you see this type of relationship, it is likely that what you think is the logic source really is an intermediate part of a larger network (or you have a circuit that is not completely logical driven, or there is a physical problem with your circuit).

In essence the actual relationships between logical elements and clocks can be reduced to a very limited set of output signals (which is good because things would be much harder if they were not - on each of the positive and negative edges of the clock (2 possibilities) the logic(high or low, 2 more possibilities) can be used to determine whether the output is high or low)... So, every single output channel can be modeled by a flip-flop, an input (logical network output), and a clock... All the complexity comes in deciding what the logical network looks like for that single output.  In practical situations it's not so easy to think this way for complex problems and so we use modeling and programming languages that allow us to design these logical networks using various collections of other networks that have some type of specific meaning to us... (which we will see later)